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SP5658
2.7GHz 3-Wire Bus Controlled Frequency Synthesiser Advance Information
Supersedes October 1996 Media IC Handbook HB3923-2 DS4064 - 4.1 March 1998
The SP5658 is a single chip frequency synthesiser designed for tuning systems up to 2.7GHz. The RF preamplifer contains a divide by two prescaler which can be disabled for applications up to 2GHz so enabling a step size equal to the comparison frequency up to 2GHz and twice the comparison frequency up to 2.7GHz. Comparison frequencies are obtained either from a crystal controlled on-chip oscillator or from an external source. The device contains two switching ports, in the 14 pin version and four in the 16 pin, together with an ``in-lock" flag output. The device also contains a varactor line disable and charge pump disable facility.
CHARGE PUMP CRYSTAL DISABLE ENABLE DATA CLOCK PORT P1/OC
1
14
DRIVE VEE
SP5658F
RF INPUT RF INPUT VCC LOCK PORT P0/OP
MP14
FEATURES s Complete 2.7GHz single chip system s Optimised for low phase noise s Selectable divide by two prescaler s Selectable reference division ratio s Charge pump disable s Varactor line disable s `In-lock' flag s Two switching ports in 14 pin version s Four switching ports in 16 pin version s Pin compatible with SP5659 I 2 C bus low phase noise synthesiserPP s ESD protection (Normal ESD handling procedures should be observed) APPLICATIONS s SAT, TV, VCR and Cable tuning systems s Communications systems
CHARGE PUMP CRYSTAL
1
16
DRIVE VEE
ENABLE DATA CLOCK PORT P3 PORT P2
SP5658S
DISABLE
RF INPUT RF INPUT VCC LOCK PORT P0/OP PORT P1/OC
MP16
Fig. 1 Pin connections - top view
ORDERING INFORMATION
SP5658F/KG/MP1S (Tubes, 14 lead SO) SP5658S/KG/MP2S (Tubes, 16 lead SO) SP5658F/KG/MP1T (Tape and Mounted) SP5658S/KG/MP2T (Tape and Mounted)
SP5658
13 RF INPUTS 14
PROGRAMMABLE DIVIDER : 2/1
PHASE COMP 13 BIT COUNT F pd F comp REFERENCE DIVIDER See Table 1 OSC 2 CRYSTAL
:-16/17
4 BIT COUNT
1 DE CHARGE PUMP CO 18 BIT LATCH DISABLE 1 BIT LATCH 3 BIT LATCH (R0,R1,R2) 1 BIT OS LATCH 16
CHARGE PUMP DRIVE
DISABLE 3 4 ENABLE 5 DATA 6 CLOCK
15 V EE DATA INTERFACE 7 P3 4 BIT LATCH AND PORT INTERFACE T0 1 BIT LATCH FLOCK
12 V CC
8 9 10 P2 P1/0C P0/OP
11 LOCK
Fig. 2 SP5658S block diagram
2
SP5658
ELECTRICAL CHARACTERISTICS
T amb = -20C to + 80C, VCC = + 4.5V to + 5.5V. Reference frequency = 4MHz. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated.
Value Characteristics Pin (SP5658S) Units Min Typ 59 52 40 Max 74 65 300 mA mA mVrms VCC =5V Prescaler enabled, DE=1 VCC =5V Prescaler disabled, DE=0 300MHz to 2.7GHz Prescaler enabled, DE=1, See Fig. 5b 80MHz Prescaler enabled, DE=1, See Fig. 5b. 100MHz to 2.0GHz Prescaler disabled, DE=0, See Fig. 5a 80MHz Prescaler disabled, DE=0, See Fig. 5a. Refer to Fig. 4 Refer to Fig. 4 Conditions
Supply current, ICC
12
RF input voltage
13, 14
13,14
100
300
mVrms
13, 14
40
300
mVrms
13,14
50
300
mVrms pF
RF input impedance RF input capacitance Data, Clock, Enable & Disable Input high voltage Input low voltage Input high current Input low current Clock Rate Clock data & enable input hysteresis
13, 14 13, 14 3,4,5,6 3 0 2
50
VCC 0.7 10 -10
V V A A kHz V Input voltage = VCC Input voltage = VEE
6 4,5,6 0.4
500
3
SP5658
ELECTRICAL CHARACTERISTICS
T amb = -20C to + 80C, VCC = + 4.5V to + 5.5V. Reference frequency = 4MHz. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Characteristics Pin (SP5658S) Min Bus Timing Data set up, tSU Data hold, tHD Enable set up, tES Enable hold, tEH Clock to enable, tCE Charge pump output current Charge pump output leakage Charge pump drive output current Oscillator temperature stability Oscillator supply voltage stability External reference input frequency External reference input amplitude Crystal frequency Crystal oscillator drive level Recommended crystal series resistance 1 1 16 2 2 2 2 2 2 100 2 200 4 45 200 1 2 2 20 500 12 3 10 nA mA ppm/C ppm/V MHz mVPP MHz mVPP Applies to 4MHz crystal only. ``Parallel resonant" crystal. Figure quoted is under all conditions including start up. Includes temperature and process tolerances. AC coupled sinewave AC coupled sinewave 4,5,6 300 600 300 600 300 ns ns ns ns ns See Fig. 3 See Fig. 3 See Fig. 3 See Fig. 3 See Fig. 3 See Table 3, V PIN1 = 2V V PIN1 = 2V V PIN16 = 0.7V Value Typ Max Units Conditions
Crystal oscillator negative resistance Comparison frequency Phase noise at phase detector
2
400 2 -142
MHz dBC/ Hz
6kHz loop BW, phase comparator freq 250kHz. Figure measured @ 1kHz offset, DSB (within loop band width). Prescaler disabled, DE=0 Prescaler enabled, DE=1 See Table 1
RF division ratio
240 480
131071 262142
Reference division ratio Output ports P0-P3 # Sink current Leakage current Lock output Sink current Leakage current 11 1 10 mA A 7,8,9,10 10 10 mA A
V PORT =0.7V V PORT =13.2V
V LOCK =0.7V, `out of lock' `in lock'
4
# Ports P2 and P3 are not available on the SP5658F.
SP5658
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to V EE at 0V
Characteristics
Pin (SP5658S)
Min
Max
Units
Conditions
Supply voltage, VCC RF input voltage RF input DC offset Port voltage Total port current Lock output DC offset Charge pump DC offset Drive DC offset Crystal DC offset Data, Clock, Enable & Disable DC offset Storage temperature Junction temperature MP14 Thermal Resistance Chip to ambient 123 C/W Chip to case 45 C/W MP16 Thermal Resistance Chip to ambient Chip to case Power consumption at V CC =5.5V ESD protection
12 13, 14 13, 14 7 - 10 7 - 10 7 - 10 11 1 16 2 3-6
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -55
7 2.5 VCC +0.3 14 6 50 VCC +0.3 VCC +0.3 VCC +0.3 VCC +0.3 VCC +0.3 +125 150
V V p-p V V V mA V V V V V C C
AC coupled as per application Port in off state Port in on state
111 41 407 ALL 2
C/W C/W mW kV
All ports off, prescaler enabled MIL-STD 883 TM 3015
FUNCTIONAL DESCRIPTION
The SP5658 contains all the elements necessary, with the exception of a frequency reference, loop filter and external high voltage transistor, to control a varicap tuned local oscillator, so forming a complete PLL frequency synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance. The RF preamplifier contains a selectable divide by two for operation above 2.0GHz. Up to 2GHz the RF input interfaces directly with the programmable divider, so eliminating degradation in phase noise due to the prescaler action. The block diagram is shown in Fig.2. The SP5658 is controlled by a standard 3-wire bus comprising data, clock and enable inputs. The programming word for the 16 pin variant contains 28 bits, four of which are used for port selection, 18 to set the programmable divider ratio and enable/disable the prescaler, bit DE, three bits to select the reference division ratio, bits R0-R2, one bit to set charge pump current, bit C0, and the remaining two bits to access test modes, bit T0, and to disable the varactor drive, bit OS. The data word for 14 pin variant is identical to 16 pin except 26 bits only are required, two of which are used for port selection. The programming format is shown in Fig. 3. The clock input is disabled by an enable low signal, data is therefore only clocked into the internal shift registers during an enable high and is loaded into the controlling buffers by an enable high to low transition. This load is also synchronised with the programmable divider so giving smooth fine tuning. The RF signal is fed to an internal preamplifier, which provides gain and reverse isolation from the divider signals. The output of the preamplifier is fed to the 2/1 selectable prescaler and then to the 17 bit fully programmable divider, which is of MN+A architecture. The M counter is 13 bit and the A counter 4. If bit DE is set to a 0 the prescaler is disabled; Note that the control function DE cannot be used dynamically. The output of the programmable divider is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. This frequency is derived either from the on board crystal controlled oscillator or from an external source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into 1 of 8 ratios as described in Table 1. The output of the phase comparator feeds the charge pump and loop amplifier section, which when used with an external high voltage transistor and loop filter integrates the current pulses into the varactor line voltage. The charge pump can be disabled to a high impedance state by the DISABLE input. The varactor drive output can also be disabled by the OS bit within the data word, so switching the external transistor `OFF' and allowing an external voltage to be written to the varactor line for tuner alignment purposes. The phase comparator also drives the lock detect circuit which generates a lock flag. `In-lock' is indicated by a high impedance state on the lock output. The programmable divider output divided by 2, F pd /2 and the comparison frequency, F comp can be switched to ports P0 and P1 respectively by switching the device into test mode. The test modes are described in Table 2.
5
SP5658
CLOCK ENABLE DATA 16 PIN VARIANT MSB 2 27 2 26 2 25 2 24 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 P3 P2 P1 P0 TO OS CO R2 R1 R0 DE FREQUENCY DATA DATA 14 PIN VARIANT MSB 2 25 2 24 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 P1 P0 TO OS CO R2 tCE tES 3V 0.7V t ES =Enable set up time t SU =Data set up time t HD =Data hold time t CE =Clock-to-enable time t EH =Enable hold time R1 R0 DE FREQUENCY DATA tEH 2
0
2
0
LSB
LSB
MSB IS TRANSMITTED FIRST
CLOCK
ENABLE
3V 0.7V
DA TA
3V 0.7V tSU tHD
216 to 20 DE R2 , R1 , R0 P3, P2, P1, P0 CO OS T0
t : Programmable divider ratio control bits : - 2 Prescaler (Enable = 1, Disable = 0) : t : Reference divider ratio control bits (see Table1) t : Port control bits t : Charge Pump current select (see Table 3) t : Drive output disable switch t : T mode enable (see Table 2) est
Fig. 3 Data format and timing
R2
R1
R0
RATIO
Comparison Frequency with a 4MHz external reference.
2MHz 1MHz 500kHz 250kHz 125kHz 62.5kHz 31.25kHz 15.625kHz
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
2 4 8 16 32 64 128 256
Table 1 Reference division ratios
6
SP5658
TO
0 0 1 0 0 1
OS
0 0 0 1 1 X
DIS
0 1 0 0 1 1
P0/OP
# # F pd/2 # # -
P1/0C
# # F comp # # -
FUNCTIONAL DESCRIPTION
NORMAL OPERATION CHARGE PUMP DISABLE NORMAL OPERATION VARACTOR LINE DISABLE CHARGE PUMP AND VARACTOR LINE DISABLE NOT PERMITTED
# CONTROLLED BY BITS P0 AND P1 WITHIN DATA WORD
Table 2 Test modes
C0
0 1 MIN 0.23 0.68
CURRENT IN mA
TYP 0.3 0.9 MAX 0.37 1.12
Table 3 Charge pump current
+j1 +j0.5 +j2
+j0.2
+j5
0
0.2
0.5
1
2
5 X
-j0.2 X
X
-j5
S11:Z0 = 50 NORMALISED TO 50
-j0.5 -j1
X
-j2
FREQUENCY MARKERS AT 100MHz, 500MHz, 1GHz AND 2.7GHz
Fig. 4 Typical input impedance
300 VIN (mV RMS INTO 50 ) 100 50 40 10 OPERA TING WINDOW
300 VIN (mV RMS INTO 50 ) 100 40 10 OPERA TING WINDOW
80 100
1000
2000
3000 3500
80 300
1000
2000
3000 3500 2700
FREQUENCY (MHz)
FREQUENCY (MHz)
Fig. 5a Typical input sensitivity (Prescaler disabled, DE=0)
Fig. 5b Typical input sensitivity (Prescaler enabled, DE=1)
7
SP5658
DOUBLE CONVERSION TUNER SYSTEMS
The high 2.7GHz maximum operating frequency and excellent noise characteristics of the SP5658 enables the construction of double conversion high IF tuners. A typical system shown in Fig.7 will use the SP5658 as the first LO control for full band upconversion to an IF of greater than 1GHz. The wide range of reference division ratios allows the SP5658 to be used both for the up converter LO with a high phase comparator frequency (hence low phase noise) and the down converter which utilises the device in a lower comparison frequency mode (which offers a fine step size).
50-900MHz
1.6GHz
38.9MHz
1650-2700MHz First LO SP5658 Second LO SP5658
Fig. 6 Example of double conversion from VHF/UHF frequencies to TV IF
+30V 4MHz 18pF 68pF 15nF 13k3 2N3904
Optional application utilising on-board crystal controlled oscillator
1 2 14 13
+5V
+12V
22k 16k 47k 2n2
REF 10n DIS CONTROL MICRO ENABLE DATA CLOCK LOCK P1
1n 1n OSCILLATOR OUTPUT 10n P0
TUNER
SP5658F
3 4 5 6 7
12 11 10 9 8
Fig. 7 Typical application, SP5658F
APPLICATION NOTES
A generic set of application notes AN168 for designing with synthesisers such as the SP5658 has been written. This covers aspects such as loop filter design and decoupling. This application note is also featured in the Media IC Handbook. A generic test/demo board has been produced which can be used for the SP5658. A circuit diagram and layout for the board is shown in Figs. 8 and 9. The board can be used for the following purposes: (A) measuring RF sensitivity performance. (B) Indicating port function. (C) Synthesising a voltage controlled oscillator. (D) Testing of external reference sources.
8
SP5658
P2 +5V C8 EXTERNAL REFERENCE SKT2 C6 10nF* *(NOT FITTED) C3 68pF
+30V +12V C9 C7/C8/C9 = 100nF R7 22K R8 C7 R9 47K C12 2n2F RF INPUT C5 1nF C10 1nF SKT1 VAR GND
C2 15nF
R6 13K3
1 2 14 13 12 11 10 9 8
16K T1 2N3904 C4 1nF
X1 4MHz C1 P1 DISABLE / REF ENABLE DATA / SDA CLOCK / SCL C13 100pF C14 100pF 18pF
3 4 5 6 7
NC NC
R1 4K7 R2 4K7 R3 4K7 R4 4K7 R5 4K7
D1 D2 D3 D4 D5 PIN NO : 7 8 LOCK C11 1nF
Fig. 8 Test board
Fig. 9 Test board (layout)
9
SP5658
LOOP BANDWIDTH
The majority of applications for which the SP5658 is intended require a loop filter bandwidth of between 2kHz and 10kHz. Typically the VCO phase noise will be specified at both 1kHz and10kHz offset. It is common practice to arrange the loop filter bandwidth such that the 1kHz figure lies within the loop bandwidth. Thus the phase noise depends on the synthesiser comparator noise floor, rather than the VCO. The 10kHz offset figure should depend on the VCO providing the loop is designed correctly, and is not underdamped.
REFERENCE SOURCE
The SP5658 offers optimal LO phase noise performance when operated with a large step size. This is due to the fact that the LO phase noise within the loop bandwidth is: phase comparator noise floor + 20 log 10
(
LO frequency phase comparator frequency
)
Assuming the phase comparator noise floor is flat irrespective of sampling frequency, this means that the best performance will be achieved when the overall LO to phase comparator division ratio is a minimum. There are two ways of achieving a higher phase comparator sampling frequency:- A) Reduce the division ratio between the reference source and the phase comparator B) use a higher reference source frequency. Approach B) may be preferred for best performance since it is possible that the noise floor of the reference oscillator may degrade the phase comparator performance if the reference division ratio is very small.
10
SP5658
VREF
VCC
500
500 CHARGE PUMP
RF INPUTS 200 OS (Output disable)
DRIVE OUTPUT
RF inputs
Loop amplifier
VCC PORT/LOCK
25K
BIAS
Disable, Enable, Data and Clock inputs
Output Ports and Lock Output
VCC
CRYSTAL
Reference oscillator
11
/O Fig. 10 Input/Output interface circuits
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